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GART

GART — From DRI wiki

PCIe&AGP graphics hardware is dedicated high-speed bus that allow the graphics controller to fetch large amount of data directly from system memory. It uses a Graphics Address Re-mapping Table to provide a physical-contiguous view of scattered pages in system memory for DMA transfers.

Main memory is specifically used for advanced three-dimensional features, such as textures, alpha buffers …

There are two primary usage models for PCIe&AGP:

  • DMA ::: In the DMA model, the primary graphics memory is the local memory associated with the accelerator, referred to as the local frame buffer. 3D structures are stored in system memory, but are not used (or executed) directly from this memory; rather they are copied to primary (local) memory (the DMA operation) to which the rendering engine’s address generator makes its references. This implies that the traffic on the AGP tends to be long, sequential transfers, serving the purpose of bulk data transport from system memory to primary graphics (local) memory. This sort of access model is amenable to a linked list of physical addresses provided by software (similar to the operation of a disk or network I/O device), and is generally not sensitive to a non-contiguous view of the memory space.
  • execute ::: In the execute model, the accelerator uses both the local memory and the system memory as primary graphics memory. From the accelerator’s perspective, the two memory systems are logically equivalent; any data structure may be allocated in either memory, with performance optimization as the only criterion for selection. In general, structures in system memory space are not copied into the local memory prior to use by the accelerator, but are executed in place. This implies that the traffic on the AGP tends to be short, random accesses, which are not amenable to an access model based on software resolved lists of physical addresses. Because the accelerator generates direct references into system memory, a contiguous view of that space is essential; however, since system memory is dynamically allocated in random 4K pages, it is necessary in the execute model to provide an address mapping mechanism that maps random 4K pages into a single contiguous, physical address space

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VGA arbiter

Definition:

When multiple video cards are uncoordinatedly using the legacy VGA interface, one card might decode messages that were not sent to it.To solve this problem, it is needed an entity that controls all the accesses made using the legacy VGA interface. In Xorg this happens when multiple instances are running. It is important to note that some GPUs can skip completely if they are able to disable their VGA decoding resource.

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  • Verify with ATI tools

fglrxinfo:

$ fglrxinfo display: :0.0 screen: 0 OpenGL vendor string: ATI Technologies Inc. OpenGL renderer string: Radeon X1600 Series OpenGL version string: 2.1.7415 Release

if the vendor string is mesa, the driver wouldn’t configure properly the /etc/X11/xorg.conf

  • Verify with Linux Tools

glxinfo:

This command line option should report “direct” rendering

Xorg.0.log:

X server log file also contains useful info about driver installation.

  • Configuring

aticonfig:

aticonfig –initial (creates device section using fglrx)

aticonfig –overlay-type=Xv (Enable Video acceleration Xv Overlay)

 

 

Arch Motherboard

To start off let’s take a look at how an computer is wired up nowadays:

There are three main ways by which the CPU and the outside communicate: memory address space, I/O address space, and interrupts.

In a motherboard the CPU’s gateway to the world is the front-side bus connecting it to the northbridge. Whenever the CPU needs to read or write memory it does so via this bus. It uses some pins to transmit the physical memory address it wants to write or read, while other pins send the value to be written or receive the value being read.

Now comes the rub. We’re used to thinking of memory only in terms of RAM, the stuff programs read from and write to all the time. And indeed most of the memory requests from the processor are routed to RAM modules by the northbridge. But not all of them. Physical memory addresses are also used for communication with assorted devices on the motherboard.These devices include video cards, most PCI cards (say, a scanner or SCSI card), and also the flash memory that stores the BIOS

When the northbridge receives a physical memory request it decides where to route it: should it go to RAM? Video card maybe? This routing is decided via the memory address map. For each region of physical memory addresses, the memory map knows the device that owns that region. The bulk of the addresses are mapped to RAM, but when they aren’t the memory map tells the chipset which device should service requests for those addresses. This mapping of memory addresses away from RAM modules causes the classic hole in PC memory between 640KB and 1MB. A bigger hole arises when memory addresses are reserved for video cards and PCI devices. This is why 32-bit OSes have problems using 5 Gigs of RAM. In Linux the file /proc/iomem neatly lists these address range mappings. The diagram below shows a typical memory map for the first 4 gigs of physical memory addresses in a PC.

Actual addresses and ranges depend on the specific motherboard and devices present in the computer, but most Core 2 systems are pretty close to the above. All of the brown regions are mapped away from RAM. Remember that these are physical addresses that are used on the motherboard buses. Inside the CPU (for example, in the programs we run and write), the memory addresses are logical and they must be translated by the CPU into a physical address before memory is accessed on the bus.

The rules for translation of logical addresses into physical addresses are complex and they depend on the mode in which the CPU is running (real mode, 32-bit protected mode, and 64-bit protected mode). Regardless of the translation mechanism, the CPU mode determines how much physical memory can be accessed. For example, if the CPU is running in 32-bit mode, then it is only capable of physically addressing 4 GB (well, there is an exception called physical address extension, but ignore it for now). Since the top 1 GB or so of physical addresses are mapped to motherboard devices the CPU can effectively use only ~3 GB of RAM (sometimes less – I have a Vista machine where only 2.4 GB are usable). If the CPU is in real mode, then it can only address 1 megabyte of physical RAM (this is the only mode early Intel processors were capable of). On the other hand, a CPU running in 64-bit mode can physically access 64GB (few chipsets support that much RAM though). In 64-bit mode it is possible to use physical addresses above the total RAM in the system to access the RAM regions that correspond to physical addresses stolen by motherboard devices. This is called reclaiming memory and it’s done with help from the chipset.

That’s all the memory we need for the next post, which describes the boot process from power up until the boot loader is about to jump into the kernel. If you’d like to learn more about this stuff, I highly recommend the Intel manuals. I’m big into primary sources overall, but the Intel manuals in particular are well written and accurate.

  • ABI

In computer software, an Application Binary Interface describes the low-level interface between an application and the OS or other application.

ABIs cover details such as data type, size, and alignment; the calling convention, which controls how functions‘ arguments are passed and return values retrieved; the system call numbers and how an application should make system calls to the operating system; and in the case of a complete operating system ABI, the binary format of object files, program libraries and so on. A complete ABI, such as the Intel Binary Compatibility Standard (iBCS), allows a program from one operating system supporting that ABI to run without modifications on any other such system, provided that necessary shared libraries are present, and similar prerequisites are fulfilled.

  • API

An application programming interface is a particular set of rules and specifications that a software program can follow to access and make use of the services and resources provided by another particular software program that implement that API. It serves as an interface between different software programs and facilitates their interaction, similar to the way the user interface facilitates interaction between humans and computers.

An API can be created for applications, libraries, operating systems, etc., as a way of defining their “vocabularies” and resources request conventions . It may include specifications for routines, data structures, object classes and protocols used to communicate between the consumer program and the implementer program of the API

  • Linux本身没有图形界面,Linux现在的图形界面的实现只是linux下的应用程序实现

图形界面并不是linux的一部分,linux只是一个基于命令行的操作系统,linux和Xfree的
关系就相当于当年的DOS和 WINDOWS3.0一样,windows3.0不是独立的操作系统,它只是DOS
的扩充,是DOS下的应用程序级别的系统,不是独立的操作系统,同样 XFree只是linux下的
一个应用程序而已.不是系统的一部分,但是X的存在可以方便用户使用电脑.WINDOWS95及
以后的版本就不一样了,他们的图形界面是操作系统的一部分,图形界面在系统内核中就
实现了,没有了图形界面windows就不成为windows了,但linux却不一样,没有图形界面lin
ux还是linux,很多装linux的WEB服务器就根本不装X服务器.这也WINDOWS和linux的重要
区别之一
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