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Posts Tagged ‘protected mode’

Protected mode

Definition:

80386+ provides many new features to overcome the deficiencies of 8086 which has almost no support for memory protection, virtual memory, multitasking or memory about 640K and still remain compatible with the 8086 family. The 386 has all the features of the 8086 and 286, with many enhancements. As in the earlier processors, there is the real mode, like 286, 386 can operate in protected mode, however, the protected mode on 386 is vastly different internally.Protected mode is not to protect your program, instead, it is to protect everyone else from your program.

Addressing:

Protected mode and real mode don’t seem to be very different. They all use memory segmentation, interrupts and device drivers to handle the hardware.

Real mode addressing

Memory is organized by 64K segments at least 16 bytes apart. Segmentation is handled through the use of an internal mechanism in conjunction with segment registers.

The contents of these segment registers(CS, DS, SS…) form part of the physical address that the CPU places on the bus address. The physical address is generated by multiplying the segment register by 16 and then add 16 bit offset. It is this 16 bit offset that limits us to 64K segments.

 

 

 

 

 

 

 
 
 
 
 
Protected Mode addressing

Segmentation is defined via a set of tables called descriptor tables.The segment registers contain pointers into these tables, there are two types of tables used to define memory segmentation:

GDT(Global Descriptor Table) and LDT(Local Descriptor Table).

The GDT contains the basic descriptors that all applications can access. In real mode, one segment is 64K big followed by the next in a 16 byte distance. In protected mode, we can have a segment as big as 4Gb and we can put it wherever we want. The LDT contains segmentation information specific to a task or program.

As OS could set up a GDT with its system descriptors and for each task an LDT with appropriate descriptors. Each descriptor is 8 bytes long. The format shows as the following figure:

Each time a segment register is loaded, the base address is fetched from the appropriate table entry. The contents of the descriptor is stored in a programmer invisible register called shadow registers so that future references to the same segment can use this information instead of reference the table each time. The physical address is formed by adding the 16 or 32 bit offsets to the base address in the shadow register.

We also have another table called interrupt descriptor table or the IDT. The IDT contains the interrupt descriptors. These are used to tell the processor where to find the interrupt handler.

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